Monday, August 20, 2012

uJTAG, Open Source minimalistic JTAG dongle

I'm releasing the design files of a JTAG dongle. JTAG is a interface designed to test printed circuit boards (PCB) using boundary scan. But today, is also used to test Integrated Circuits (IC), in particular this interface is present in all (I think) ARM processors.

The JTAG dongle I designed, named uJTAG, is a minimalistic implementation with a 6 pin connector in contrast to the standard 20 pin connector. The purpose of this dongle is to flash and debug ARM microcontrollers. Especifically, this dongle has been tested with STM32 microcontrollers.

uJTAG old version

On the above image you can see the previous version of uJTAG I implemented. In the current version, I have removed the EEPROM memory, which I later figured was not necessary, as the default USB <-> UART configuration is enough. Also the components have been moved to the top layer.

PINOUT


As I mentioned previously the JTAG standard specifies a 20 pin connector shown below:

VDD VDD
 (optional)
TRST GND
TDI GND
TMS GND
TCK GND
RTCK GND
TDO GND
RESET GND
NC GND
NC GND

uJTAG connector uses only 6 pins. Pinout is shown below:

TMS
TDI
TDO
TCK
GND
VDD

These four signals (TMS, TDI, TDO, TCK) are the minimum necessary to use JTAG on microcontrollers. Actually, the RESET signal is also important, but with these signals a RESET can be issued by software, i.e. as a combination of the other 4 signals.

USE


I use this JTAG dongle with STM32 microcontrollers, specifically I use it with F4Dev, an open source development board for STM32F4 microcontrollers, and with openOCD 0.5.0., a software that enables a transparent JTAG communication from PC to microcontroller/processor via the USB protocol.

uJTAG mated with F4Dev


REPOSITORY


You can find all the design files in this repository.

6 comments:

  1. Hi,

    I want to integrate a small onboard debugger into an arm board i'm making and I like your simple approach, so i have a few small questions...

    1) You don't have line drivers for the TMS/TDO.. pins, are they necessary in general?
    CoLink jtag dongle has buffer on the outputs, http://www.coocox.org/CoLinkGuide/CoLinkDIY.htm
    I see that no level translators are needed because both there FTDI and stm32 run at 3V3 but the buffers confuse me.

    2)What function does the eeprom provide with the FT2232h and how were you able to remove it? Does the ft2232h device startup as a USB-UART then openOcd configures via software the JTAG functionality? Not needing the eeprom?

    3)Does the software perform the reset, not needing the TRST signal at all? I've seen it come out on ADBUS0 in other designs but no reference to that in the datasheet. Is this an OpenOcd thing?

    Thanks again.
    Tom

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    Replies
    1. Hello Tom,

      It's great to hear that you are considering uJTAG for the board you are designing. Regarding your questions:

      1) The buffers (same voltage level) are for 'protection' (in case of logic/bus contention) and less capacitive/current load on the FTDI. Some designs, like the Bus Blaster, use a 'smart' level translator for compatibility with 1.8V-3.3V targets.

      ** I decided to drop the protection to minimize the part count.

      2) Each channel of the The FTDI device can work as USB <-> UART (default), 245 FIFO, MPSSE, FT1248, etc. Without the EEPROM, the FTDI device will work as a USB <-> UART, you need the EEPROM to select other configuration (like 245 FIFO, MPSSE, etc)

      The USB <-> UART configuration can be used in a bit-bang fashion (i.e. the UART lines can be used as GPIO) using libusb/libftdi. The OpenOCD interface implements the JTAG protocol using this bitbang mode.

      ** In conclusion, the EEPROM is not necessary if you are using the OpenOCD interface, as a bonus you can also use the uJTAG as a USB <-> UART translator.

      3) The JTAG specification allows resetting the target without a dedicated TRST signal, using a combination of the other signals. And yes, OpenOCD supports this option called "software reset".

      ** Therefore, no dedicated TRST signal is necessary if the software reset can be used.

      I used the FT232H, which only has one channel, as I only needed one JTAG flasher/debugger. This selection reduced part count and board complexity compared to the 'standard' election of the FT2232H.

      I don't know what target are you going to use the JTAG with, but you might want to check the RTCK signal for adaptive clocking. That signal is not available on the uJTAG.

      Finally, I must say I've used uJTAG successfully with STM32F4 uCs that run at 24MHz-168MHz.

      I wish you the best on your project.

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    2. Thanks alot, cleared things up :)

      One question though, on the datasheets it says that MPSSE can be configured through software. Does openOcd using the MPSSE to form the jtag interface or does it do it synthetically through GPIO pins?

      Thanks
      Tom

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    3. Yes, MPSSE can be configured with software, but that configuration needs to be stored in the EEPROM attached to the FTDI device.

      OpenOCD doesn't use the MPSSE, instead it uses the default USB <-> UART configuration (no EEPROM needed) in bit bang ("GPIO") mode.

      I *think* you can use the MPSSE to do the USB <-> JTAG translation, but you'll need to write a software akin to OpenOCD to make it work. Also you'll need the EEPROM to configure the FTDI device to use the MPSSE instead of the default USB <-> UART.

      Now, implementing the JTAG on the MPSSE *might* be "faster" (probably, not that noticeable) than the OpenOCD bit bang solution, but it requires hard work from your part, as new software is needed.

      Delete
  2. Excellent, thats much clearer now. Thanks for your help and simple design.

    Tom

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  3. Hello,

    Would it be possible to show the openocd config file?
    I would like to use a FT232H as OpenOCD debugger but can't get it to work :S

    Rik

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